Single Electron Encoded SET Memory Elements

Abstract— The ability to control the transport of individual electrons in Single Electron Tunneling (SET) based circuits creates the conditions for Single Electron Encoded Logic (SEEL). The logic values and of SEEL gates are encoded as a net charge of or electron charges. This paper investigates the implementation of SEEL memory elements based on SEEL Boolean logic gates. After the introduction of the SEEL Boolean logic gates that serve as basic building blocks, SEEL implementations of the RS-latch, D-latch and positive edge-triggered D flip-flop are proposed and verified by simulation. Finally, the area, switching delay and power consumption of the memory elements are compared with CMOS-like SET transistor based implementations. The comparison indicates that the total circuit area is comparable, but the SEEL Boolean gate based implementations reduce both delay and power consumption by a factor of . Keywords— single electron technology, SET, single electron encoded logic, memory elements